RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design

Specifications

Book Description

The SystemVerilog Hardware Description Language (HDL) is utilized by engineers in the design of FPGAs and ASICs. This ebook serves as both a reference and a tutorial for those engineers. The document titled “RTL Modeling with SystemVerilog for Simulation and Synthesis” (PDF) demonstrates how to write SystemVerilog models at the Register Transfer Level (RTL) that simulate and synthesize in an appropriate manner. The document places an emphasis on appropriate coding styles and best practices.

SystemVerilog is the newest generation of the original Verilog language, and it includes many important capabilities to model increasingly complex designs in a competent and accurate manner. SystemVerilog is the newest generation of the Verilog language. The SystemVerilog-2012/2017 standards have been incorporated into this ebook.

This ebook is intended for engineers who are either already knowledgeable about digital design engineering or who are currently studying it. This ebook does not present the theory behind digital design; rather, it demonstrates how to apply that theory in order to write RTL models that correctly simulate and synthesize. (Note: Compared to the author's older ebook titled “SystemVerilog for Design,” this book offers a more in-depth analysis of the RTL modeling aspects of SystemVerilog. The older ebook was written for a readership that already has a working knowledge of the Verilog-2001 programming language, and it only includes the enhancements that SystemVerilog brings to the table in comparison to Verilog-2001. This book covers the entirety of the combined Verilog and SystemVerilog programming language, with a particular emphasis on the most effective coding styles for simulation and synthesis.

Phil Moorby, the creator of the first version of the Verilog programming language, has the following to say about this ebook (this is an excerpt from the Foreword of the ebook): “Many distributed textbooks on the design side of SystemVerilog make the assumption that the reader is already familiar with Verilog; they then proceed to simply describe the new extensions.” It is time to move on from the stepping stones and instruct a single language that is clear and consistent through the use of a single ebook. In fact, you should probably not even refer to the older practices at all! This ebook is an excellent resource for learning the design aspects of SystemVerilog, and if you are a designer of digital systems or a verification engineer looking for bugs in these designs, then you will find that using SystemVerilog will provide you with significant benefits.

PLEASE TAKE NOTE That the only thing that comes with this product is a PDF version of the ebook “RTL Modeling with SystemVerilog for Simulation and Synthesis.” There are no access codes contained within.